In project A03 we investigate the transport properties of the topological insulator material HgTe. Since transport in topological insulators (TIs) is very sensitive to surface treatments and damages, a strong emphasis is directed onto the device fabrication. Thus, during the past funding periods the aim was to develop fabrication processes which allowed to reduce thermal and mechanical stress as well as the exposure time to high energy electrons or ions. The major achievements in this respect were a wet-chemical etching process which is suitable for device sizes down to 100 nm and a low-temperature atomic layer deposition process suitable for gate insulator fabrication which helped to improve the yield of microstructured devices and improved the transport properties significantly. For the coming funding period the optimization of the fabrication processes is an ongoing task. One further step will be the use of a less invasive optical maskless lithography (micro writer) tool which became available during the second funding period. The implementation of the new micro writer tool reduces the hazard for surface damages and strain related to conventional masked based Figure 1: Gate voltage (Vg ) dependent conductance of 100 nm wide quantum point contacts for different quantum well thicknesses (a) d = 7 nm, d = 5.5, and (b) d = 10.5 nm, measured at T = 1.4 K. exposure techniques, and may replace e-beam lithography for many sample designs. However, the involved process steps still have to be adapted for HgTe and optimized. For the envisioned transport investigations two lithographic developments are especially impor- tant: reliable ohmic contacts which sustain high magnetic fields and a split-gate technology. The latter consists of a separation between gate structures of less than 100 nm which allows for a controlled connection between topological insulator states and normal states. A first device application for split- gates within this project will be in connection with quantum point contacts(QPCs). Recent experiments demonstrated that for certain quantum well (QW) structures an unexpected quantization plateau of only one conducting mode is observed, the origin of which was theoretically explored by A09. However, the device design did not allow for an unambiguous interpretation. With the help of three separately controllable gates, injector - QPC - detector, the involved edge channel interaction will be explored. A multi-gate structure will be the basis for further applications using the spin-selectivity of heli- cal edge channels and the transmission control of quantum point contacts. Connecting two QPCs in series is a template for the realization of a quantum spin-Hall interferometer. A ring between both QPCs is formed by helical edge channels when the area is gated into the quantum spin Hall (QSH) regime. The efficiency of the interference controlled transmission will be explored. A further step towards a spin controlled transistor can be achieved by using the spin selectivity of helical edge channels as injector and detector where the active area in-between is used for spin manipulations related to the Rashba spin orbit (SO) interaction, where the Rasha SO interaction strength is con- trollable externally via an applied gate voltage. The feasibility of potential device applications will be explored in the coming funding period. Investigations of the hydrodynamic electron flow in Dirac surface states will be continued. Especially since important improvements of the sample quality i.e., the carrier mobility, have been achieved recently. The feasibility to establish hydrodynamic flow conditions in HgTe 2D and 3D Dirac systems has now become comparable to other well-known materials like GaAs and graphene. Apart from demonstrating the expected temperature dependent transport properties in an electron channel, the feasibility of further transport properties, which are predicted by projects A06, A09, and C09 within the SFB 1170, will be explored by project A03.